1. Field of the Invention
The present invention generally relates to a method for simultaneously dicing a plurality of chips on a wafer to achieve singulation (separation) of semiconductor chip products from parent wafers at the end of the wafer level fabrication process.
2. Description of the Related Art
The industry standard methodology for dicing semiconductor wafers into chips currently involves a mechanical saw that has a blade width that is typically on the order of 50 μm. The mechanical saw can be used alone, or for more advanced technology products, in combination with a laser that cuts an initial scribe line at the edge of each die in an effort to limit the probability of long-range saw-induced crack propagation from the kerf area into the chip edge. For modern and advanced generation Back-End-Of-The-Line (BEOL) technology products, the integration of copper and Low-K dielectric materials results in a mechanically fragile structure comprised of sensitive interfaces which can be easily compromised by chip edge damage, despite the use of metal-stack crackstop structure. This can lead to serious reliability problems, particularly in high stress plastic-packaged parts which employ Controlled Collapse Chip Connection (C4) solder connections.
In 3-D chip stacking applications, integrated circuit wafers are typically thinned by a backside grind process to 100 um or less prior to the dicing singulation process. The dicing of these thinned structures is even more delicate an operation than for the full ˜780 μm wafer.
The blade width of the dicing saw together with the room required for the standard moisture oxidation barrier/crackstop structure drive a requirement for a sizable kerf width and chip edge space allocation (in layout) to accommodate them. Even so, the attendant reliability risk due to mechanically induced chip edge cracking remains a concern.
Conventional processes for 3-D chip stacking application currently use the idea of a polysilicon “moat” around the chip, to function merely as a crackstop. In this invention, this original crackstop structure is supplemented with a separate crackstop structure of a particular design (i.e., having a vertical coincidence w/BEOL (back-end-of-line) chip crackstop structure), that is used to effect die singulation. The original polysilicon crackstop, may still be used in addition as a crackstop or may be eliminated altogether.
There is a need for a singulation process that does not require the use of a mechanical saw. This is eminently possible for the chip stacking application, in which wafer processing is done on both sides of the wafer as part of the normal process for the creation of through-silicon vias (TSVs).